In some integrated circuit applications, it is desirable to include dispersed single bit EPROM cells, as distinguished from multi-bit EPROM cell arrays, in the integrated circuit architecture. For example, EPROM BIT cells may be employed as trim elements in high voltage applications. It is important that all EPROM BIT cells dispersed across an IC wafer meet a common reliability specification.
EPROM BIT cells are commonly fabricated based upon a P-type MOSFET device that utilizes a single layer of polysilicon (single poly). FIGS. 1A and 1B show a conventional EPROM BIT cell structure 100. The EPROM BIT cell structure 100 includes an N-type epitaxial layer 102 that has been grown on an underlying semiconductor substrate 104, typically P-type crystalline silicon. An N-type buried layer 106 is formed at the interface between the substrate 104 and the epitaxial layer 102. An N-type well 108 is formed in the epitaxial layer 102. Isolation oxide 110, typically “local oxidation of silicon” (LOCOS) oxide, is formed at the periphery of the N-well 108 to define an active device region. The LOCOS 110 extends in the direction of the arrow in FIG. 1B to the next device isolation. That is, the EPROM device region is surrounded by LOCOS field oxide on all sides. Thus, an isolated EPROM cell is surrounded by an extremely large field oxide that has been rapidly grown, using a high pressure oxidation process, to a thickness of ˜10.5 kA. Mechanical stress is caused in the EPROM active channel region. Mechanical stress altered changes in the SiO2/Si barrier height influence charge leakage from the floating gate
as stated above, an EPROM BIT cell, that is, a PMOS transistor with a floating gate, is formed in the active device region. More specifically, as shown in FIG. 1B, a gate oxide layer 112 is formed on the upper surface of the N-well 108. A conductive floating gate 114, typically N-doped polysilicon, is formed on the gate oxide layer 112. The FIG. 1B structure 100 shows oxide spacers 116 formed on the sidewalls of the N-doped poly gate 114. A P+ source region 118 is formed in the N-well 108 at one side of the floating gate 114. A P+ drain region 120 is formed in the N-well 108 at the other side of the floating gate 114 to be spaced apart from the source region 118 to define a n-channel region therebetween. As shown in FIG. 1B, the floating gate 114 overlies the n-channel region. An N+ body contact region 122 is formed in the N-well 108 between the source region 118 and the LOCOS isolation oxide 110. FIG. 1B further shows a Metal 1 interconnect layer 124 that is formed over the EPROM BIT cell structure and separated therefrom by intervening dielectric material 126. Conductive contacts 128 extend through the dielectric layer 126 to provide electrical contact between the source region 118, the body contact region 122 and the drain region 120. As shown in FIG. 1B, the source and body contacts are butted, i.e., there are no separate contacts to the source and body. The Metal1 from the source connect shields the floating gate 114; while this scheme does not impact data retention, it does tighten the initial read current from the EPROM BIT cell 100. The initial read of an un-programmed cell of this type is done by applying a source-drain potential of 1V. The typical value of an un-programmed cell read current is 15 nA. Those skilled in the art will appreciate that the above-described EPROM BIT cell structure may be fabricated utilizing well known integrated circuit processing techniques.
Because the gate of the PMOS transistor is floating in the above-described EPROM BIT cell, it can be used as a charge storage device. Charge injection into the floating gate is done by applying a minimum source-drain potential of 8V. This bias causes a programming current of at least 350 μA to flow through the device. The programming current is a result of a combination of capacitive coupling between the source and the floating gate, drain-induced barrier lowering, and punch-through. This hole current generates electrons in the drain's high field region by impact ionization. The resulting electrons are then injected into the gate oxide and accumulated in the floating gate. This negative gate charge induces a conductive inversion layer at the Si/SiO2 interface of the PMOS device, and the device becomes essentially a depletion-mode transistor.
Read of the programmed EPROM cell is done by applying a source-drain bias of 1V. The read current of a programmed cell is approximately 80 μA at time zero (i.e., prior to bake).
After bake at 250° C. for 86 hours, the EPROM cell should not lose more than 50% of the initial programmed charge in order to reliably distinguish between programmed and un-programmed EPROM BIT cells.
The isolation process utilized for the above-described single poly, PMOS EPROM cell is LOCOS field oxide. The field oxide is grown with high pressure oxidation, which creates stress in the silicon substrate due to the rapid field oxide growth. The region of the EPROM cell where the poly floating gate of the EPROM cell lies on the edge of the LOCOS field oxide's well known “bird's beak” is the region of maximum stress in silicon. Potentially, a local weakness in the gate oxide is created, providing a path for charge leakage to the substrate through the locally weak gate oxide. For the isolated EPROM BIT cell, there is a very large field oxide region surrounding the cell and is worst case for stress in silicon. The EPROM cell is susceptible to charge loss of over 50% at wafer edge, which is creates unacceptable condition in which to distinguish a programmed cell from an un-programmed cell. LOCOS oxidation on a high voltage process with a thick field oxide requirement sensitizes the mechanism. Stress could also come from other isolation processes, like shallow trench isolation (STI), or other oxidation and dielectric deposition processes. Advanced processes may use STI isolation for EPROM BIT cells.
Experimental data showing that compressive stress degrades retention time for non-volatile memory devices may be found in a publication by R. Arghavani et al. titled “Strain Engineering to Improve Data Retention Time in Nonvolatile Memory” (IEEE Transactions on Electron Devices, Vol. 54, No. 2, February 2007).